Articles

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

[+] Author Affiliations
Jun Wang

University of Hong Kong, Department of Electrical and Electronic Engineering, Pokfulam Road, Hong Kong E-mail: junwang@eee.hku.hk

Alfred K. Wong

Fortis Systems, Inc., Brookline, Massachusetts 02445

Edmund Y. Lam

University of Hong Kong, Department of Electrical and Electronic Engineering, Pokfulam Road, Hong Kong

J. Micro/Nanolith. MEMS MOEMS. 4(1), 013001 (Mar. 16, 2005). doi:10.1117/1.1857529
History: Received May 2, 2004; Revised Jun. 30, 2004; Accepted Jul. 9, 2004; Mar. 16, 2005; Online March 16, 2005
Text Size: A A A

The practicability and methodology of applying resolution-enhancement-technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from −4.2 to −15.8% with the four fabrication-friendly layout approaches. The area change of five test circuits using the four approaches range from −16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Photo-Optical Instrumentation Engineers.

© 2005 Society of Photo-Optical Instrumentation Engineers

Citation

Jun Wang ; Alfred K. Wong and Edmund Y. Lam
"Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates", J. Micro/Nanolith. MEMS MOEMS. 4(1), 013001 (Mar. 16, 2005). ; http://dx.doi.org/10.1117/1.1857529


Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging & repositioning the boxes below.

Related Book Chapters

Topic Collections

PubMed Articles
Advertisement
  • Don't have an account?
  • Subscribe to the SPIE Digital Library
  • Create a FREE account to sign up for Digital Library content alerts and gain access to institutional subscriptions remotely.
Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).
Access This Proceeding
Sign in or Create a personal account to Buy this article ($15 for members, $18 for non-members).
Access This Chapter

Access to SPIE eBooks is limited to subscribing institutions and is not available as part of a personal subscription. Print or electronic versions of individual SPIE books may be purchased via SPIE.org.