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Fabrication and testing investigation of low-voltage integrated electrophoresis chip based on silicon-on-insulator-MEMS

[+] Author Affiliations
Yi Xu

Chongqing University, Chemistry and Chemical Engineering College and Microsystems Research Center, Shazhengjie Street No. 174, Chongqing, China, 400044

Ji W. Shen, Jia L. Lu

Chongqing University, Chemistry and Chemical Engineering College, Shazhengjie Street No. 174, Chongqing, China, 400044

Zhi Y. Wen

Chongqing University, Microsystems Research Center, Shazhengjie Street No. 174, Chongqing, China, 400044

J. Micro/Nanolith. MEMS MOEMS. 6(3), 033009 (August 13, 2007). doi:10.1117/1.2770459
History: Received August 01, 2006; Revised May 11, 2007; Accepted May 15, 2007; Published August 13, 2007
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A new approach has been developed to fabricate a low-voltage integrated electrophoresis chip based on silicon-on-insulator micro electron mechanical systems (SOI-MEMS). Arrayed-electrodes are embedded along the microchannel sidewall in the designed microchip. Because voltage should be applied effectively to arrayed-electrodes to serve as the driving force for the on-microchip electrophoresis, electrical isolation between arrayed-electrodes is essential for a practicable low-voltage integrated electrophoresis chip. Fabrication of arrayed-electrodes becomes the critical technique that governs the performance of the low-voltage integrated electrophoresis chip. Combined with the SOI substrate, full dielectric isolation is proposed to obtain high-performance integrated three-dimensional (3-D) sidewall arrayed-electrodes. The fabrication processes mainly consist of SOI wafer fabrication, narrow trench etching, polysilicon refilling and planarization, boron diffusion to form arrayed-electrodes, elicitation and protection of arrayed-electrodes, dry etching to obtain reservoirs and microchannels, etc. In order to obtain high-quality electrical isolation between arrayed-electrodes, process experiments were conducted to obtain optimized operational parameters. Poly (dimethylsiloxane) (PDMS) was selected as a cover to achieve a hybrid electrophoresis chip. The validity of the hybrid electrophoresis chip was tested by amino acid separation. Results showed high performance of the fabricated low-voltage integrated electrophoresis chip based on SOI-MEMS.

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© 2007 Society of Photo-Optical Instrumentation Engineers

Citation

Yi Xu ; Ji W. Shen ; Jia L. Lu and Zhi Y. Wen
"Fabrication and testing investigation of low-voltage integrated electrophoresis chip based on silicon-on-insulator-MEMS", J. Micro/Nanolith. MEMS MOEMS. 6(3), 033009 (August 13, 2007). ; http://dx.doi.org/10.1117/1.2770459


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