The only lithography technology that is readily available and has a full infrastructure is double patterning with ArF immersion scanners. Single patterning is being used for applications with k1 between 0.26 and 0.3. In principle, double patterning can reduce k1 by half. This means memory products at half pitches below 19 nm and at least 15-nm nodes for logic products. Unfortunately, double patterning is costly. Not only are exposure and mask costs doubled, the cost for pattern transfer, such as etching, is also doubled. In addition, the circuit patterns need additional restrictions to confine the splitting to only two masks. If left unrestricted, three or even four masks may be needed, further escalating the cost. Needless to say, the overlay accuracy between exposures adds an extra requirement to the exposure tool.