Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to in width are fabricated using spacer-defined features. A multitiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultradense circuit integration for regular layouts.