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Fabrication and electrical characterization of through-Si-via interconnect for 3-D packaging

[+] Author Affiliations
Jong-Woong Kim, Seung-Boo Jung

Sungkyunkwan University, School of Advanced Materials Science & Engineering, 300 Cheoncheon-dong, Jangan-gu, Suwon 440-746, Korea

J. Micro/Nanolith. MEMS MOEMS. 8(1), 013040 (February 17, 2009). doi:10.1117/1.3081417
History: Received June 30, 2008; Revised November 25, 2008; Accepted December 19, 2008; Published February 17, 2009
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Fabrication process of through-Si-via (TSV) interconnects and their electrical characterization method were investigated for 3-D stacked packaging. A prototype, three-layer module with a flip-chip bonding process with anisotropic conductive film (ACF) was fabricated with the process. To measure a single interconnect resistance, a Kelvin structure was designed and applied on the chip and substrate. A theoretical model to calculate the connection resistance of the 3-D TSV interconnects was also derived and used to verify the experimentally measured resistance by applying the Kelvin structure designed. Optimum conditions for the formation of through-holes with the deep reactive ion-etching process were a coil power of 200W, cycle time of 6.55s, and SF6:C4F8 gas flow rate of 260:100sccm. Pulse-reverse current provided the finest grain growth during the Cu electroplating and thus prevented the trapping of voids. The experimentally measured resistance was successfully verified by the theoretical model, and the model shows that the resistance value was mainly contributed by the ACF interconnect, not by TSVs.

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© 2009 Society of Photo-Optical Instrumentation Engineers

Citation

Jong-Woong Kim and Seung-Boo Jung
"Fabrication and electrical characterization of through-Si-via interconnect for 3-D packaging", J. Micro/Nanolith. MEMS MOEMS. 8(1), 013040 (February 17, 2009). ; http://dx.doi.org/10.1117/1.3081417


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