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Application results of lot-to-lot high-order and per-shot overlay correction for sub-60-nm memory device fabrication

[+] Author Affiliations
Jangho Shin

Samsung Electronics Corporation, Semiconductor R&D, Hwasung-City, Gyeonggi-Do, Korea 445-701

Sangmo Nam

Samsung Electronics Corporation, Semiconductor R&D, Hwasung-City, Gyeonggi-Do, Korea 445-701

Taekyu Kim

Samsung Electronics Corporation, Semiconductor R&D, Hwasung-City, Gyeonggi-Do, Korea 445-701

Yong-Kug Bae

Samsung Electronics Corporation, Semiconductor R&D, Hwasung-City, Gyeonggi-Do, Korea 445-701

Junghyeon Lee

Samsung Electronics Corporation, Semiconductor R&D, Hwasung-City, Gyeonggi-Do, Korea 445-701

J. Micro/Nanolith. MEMS MOEMS. 8(3), 033008 (August 21, 2009). doi:10.1117/1.3210241
History: Received January 29, 2009; Revised June 10, 2009; Accepted July 08, 2009; Published August 21, 2009
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According to the International Technology Roadmap for Semiconductors 2008 (http: www.itrs.net) overlay error should be controlled under 12nm for sub-60-nm memory devices. To meet such a tight requirement, lot-to-lot high-order wafer correction (HOWC) and per-shot correction (PSC) is evaluated for the gate and contact layers of dynamic random access memory. A commercial package is available from scanner makers, such as ASML, Canon, and Nikon. In this study, HOWC is investigated for wafer correction, whereas PSC is considered for scan direction-dependent overlay correction. Experimental results verify 13nm of overlay improvement by applying HOWC. However, the amount of improvement is layer (process) dependent. It turned out that HOWC is not an overall solution. It should be applied carefully for certain process conditions. In addition, if scan direction is different (mixture of up, down, left, right) due to wafer stage routing path, then overlay performance could be degraded. To solve this problem, PSC is also evaluated. Detailed experimental results are discussed.

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© 2009 Society of Photo-Optical Instrumentation Engineers

Citation

Jangho Shin ; Sangmo Nam ; Taekyu Kim ; Yong-Kug Bae and Junghyeon Lee
"Application results of lot-to-lot high-order and per-shot overlay correction for sub-60-nm memory device fabrication", J. Micro/Nanolith. MEMS MOEMS. 8(3), 033008 (August 21, 2009). ; http://dx.doi.org/10.1117/1.3210241


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