As design rule continues to shrink, resolution enhancement techniques (RET) such as optical proximity correction (OPC) become more and more complex to enable design printability. As we know, typically integrated circuit (IC) layouts are simple shapes such as rectangles. However, high spatial frequency components of the mask spectrum that are not captured by the low-pass pupil result in a rounded image. In addition, the diffusion process in the postexposure bake (PEB) step makes the wafer rounding effects worse. This means that it is difficult to get the wafer image to match the design exactly at corners, even with the most aggressive OPC methodology. Therefore, pre-OPC site placement optimization is necessary to achieve high quality wafer images. In this work, a contour-based OPC methodology is proposed to minimize the time consumption in pre-OPC simulation site placement optimization and OPC job running. Rounded target contours that best describe the real intended wafer result are used as the target during OPC correction. By comparing classical OPC recipe-driven target point placement and contour-based OPC methodology, it is found that contour-based OPC methodology can achieve comparable image quality in a shorter turn around time (TAT) with fewer engineer resources.