Articles

Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis

[+] Author Affiliations
Valeriy Sukharev

Mentor Graphics Corporation, 1001 Ridder Park Drive, San Jose, California 95131

Ara Markosian

Mentor Graphics Corporation, 1001 Ridder Park Drive, San Jose, California 95131

Armen Kteyan

Mentor Graphics Corporation, 13A Vagharshyan Street, Yerevan 0012, Armenia

Levon Manukyan

Mentor Graphics Corporation, 13A Vagharshyan Street, Yerevan 0012, Armenia

Nikolay Khachatryan

Mentor Graphics Corporation, 13A Vagharshyan Street, Yerevan 0012, Armenia

Jun-Ho Choy

Mentor Graphics Corporation, 1001 Ridder Park Drive, San Jose, California 95131

Hasmik Lazaryan

Mentor Graphics Corporation, 13A Vagharshyan Street, Yerevan 0012, Armenia

Henrik Hovsepyan

Mentor Graphics Corporation, 13A Vagharshyan Street, Yerevan 0012, Armenia

Seiji Onoue

Toshiba Corporation, Corporate Manufacturing Engineering Center, 33 Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa 235-0017, Japan

Takuo Kikuchi

Toshiba Corporation, Corporate Manufacturing Engineering Center, 33 Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa 235-0017, Japan

Tetsuya Kamigaki

Toshiba Corporation Semiconductor Company, Advanced Memory Development Center, Kawasaki, Japan

J. Micro/Nanolith. MEMS MOEMS. 8(4), 043007 (December 04, 2009). doi:10.1117/1.3268422
History: Received April 17, 2009; Revised September 09, 2009; Accepted October 09, 2009; Published December 04, 2009; January 20, 2010
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A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabrication-defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the “standard” process-aware design optimization.

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© 2009 Society of Photo-Optical Instrumentation Engineers

Citation

Valeriy Sukharev ; Ara Markosian ; Armen Kteyan ; Levon Manukyan ; Nikolay Khachatryan, et al.
"Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis", J. Micro/Nanolith. MEMS MOEMS. 8(4), 043007 (December 04, 2009). ; http://dx.doi.org/10.1117/1.3268422


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