Articles

22-nm-node technology active-layer patterning for planar transistor devices

[+] Author Affiliations
Ryoung-han Kim

GlobalFoundries, 255 Fuller Road, Albany, New York 12203

Steven Holmes, Scott Halle

IBM Research, 255 Fuller Road, Albany, New York 12203

Vito Dai

GlobalFoundries, 1050 East Arques Avenue, Sunnyvale, California 94085

Jason Meiring

IBM Semiconductor Research and Development Enablement Center, 2070 Route 52, Hopewell Junction, New York 12533

Aasutosh Dave

Mentor Graphics Corporation, 1001 Ridder Park Drive, San Jose, California 95131

Matthew E. Colburn

IBM Research, 255 Fuller Road, Albany, New York 12203

Harry J. Levinson

GlobalFoundries, 1050 East Arques Avenue, Sunnyvale, California 94085

J. Micro/Nanolith. MEMS MOEMS. 9(1), 013001 (February 02, 2010). doi:10.1117/1.3302125
History: Received April 16, 2009; Revised November 06, 2009; Accepted December 14, 2009; Published February 02, 2010; Online February 02, 2010
Text Size: A A A

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1μm2 and other critical features across the chip with a process window are demonstrated.

Figures in this Article
© 2010 Society of Photo-Optical Instrumentation Engineers

Citation

Ryoung-han Kim ; Steven Holmes ; Scott Halle ; Vito Dai ; Jason Meiring, et al.
"22-nm-node technology active-layer patterning for planar transistor devices", J. Micro/Nanolith. MEMS MOEMS. 9(1), 013001 (February 02, 2010). ; http://dx.doi.org/10.1117/1.3302125


Tables

Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging & repositioning the boxes below.

Related Book Chapters

Topic Collections

Advertisement


 

  • Don't have an account?
  • Subscribe to the SPIE Digital Library
  • Create a FREE account to sign up for Digital Library content alerts and gain access to institutional subscriptions remotely.
Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).
Access This Proceeding
Sign in or Create a personal account to Buy this article ($15 for members, $18 for non-members).
Access This Chapter

Access to SPIE eBooks is limited to subscribing institutions and is not available as part of a personal subscription. Print or electronic versions of individual SPIE books may be purchased via SPIE.org.