Articles

Electrical assessment of lithographic gate line-end patterning

[+] Author Affiliations
Puneet Gupta

University of California, Los Angeles, Electrical Engineering Department, Los Angeles, California 90095

Kwangok Jeong

University of California, San Diego, Electrical and Computer Engineering Department, La Jolla, California 92093

Andrew B. Kahng

University of California, San Diego, Electrical and Computer Engineering Department and Computer Science and Engineering Department, La Jolla, California 92093

Chul-Hong Park

Samsung Electronics Co., Ltd., Semiconductor R&D Center, CAE Team, NRD Building, Hwasung-City, Gyeonggi-Do, Korea

J. Micro/Nanolith. MEMS MOEMS. 9(2), 023014 (June 22, 2010). doi:10.1117/1.3452319
History: Received February 17, 2010; Revised April 23, 2010; Accepted May 04, 2010; Published June 22, 2010; Online June 22, 2010
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Line-end pullback is a major source of patterning problems in low-k1 lithography. Lithographers have been well-served by geometric metrics such as critical dimension (CD) at a gate edge; however, the ever-rising contribution of line-end extension to layout area necessitates reduced pessimism in qualification of line-end patterning. Electrically aware metrics for line-end extension can be helpful in this regard. The device threshold voltage is, with nominal patterning, a weak function of line-end shapes. However, the electrical impact of line-end shapes can increase with overlay errors, since displaced line-end extensions can be enclosed in the transistor channel, and nonideal line-end shape will manifest as an additional gate CD variation. We propose a super-ellipse parameterization that enables exploration of a large variety of line-end shapes. Based on a gate capacitance model that includes the fringe capacitance due to the line-end extension, we model line-end-dependent incremental current ΔIon and ΔIoff to reflect inverse narrow width effect. Last, we calculate the Ion and Ioff considering line-end shapes as well as line-end extension length, and we define a new electrical metric for line-end extension—namely, the expected change in Ion or Ioff under a given overlay error distribution. Our model accuracy is within 0.47% and 1.28% for Ion and Ioff, respectively, compared to 3-D TCAD simulation in a typical 45-nm process. Using our proposed electrical metric, we are able to quantify the electrical impact of optical proximity correction, lithography, and design rule parameters, and we can quantify trade-offs between cost and electrical characteristics.

© 2010 Society of Photo-Optical Instrumentation Engineers

Citation

Puneet Gupta ; Kwangok Jeong ; Andrew B. Kahng and Chul-Hong Park
"Electrical assessment of lithographic gate line-end patterning", J. Micro/Nanolith. MEMS MOEMS. 9(2), 023014 (June 22, 2010). ; http://dx.doi.org/10.1117/1.3452319


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