Articles

Measurement and optimization of electrical process window

[+] Author Affiliations
Tuck-Boon Chan

University of California, Electrical Engineering Department, Los Angeles, California 90095

Abde Ali Kagalwalla

University of California, Electrical Engineering Department, Los Angeles, California 90095

Puneet Gupta

University of California, Electrical Engineering Department, Los Angeles, California 90095

J. Micro/Nanolith. MEMS MOEMS. 10(1), 013014 (February 25, 2011). doi:10.1117/1.3545822
History: Received July 19, 2010; Accepted December 30, 2010; Revised December 21, 2010; Published February 25, 2011; Online February 25, 2011
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A process window is a collection of values of process parameters that allow a circuit to be printed and to operate under desired specifications. A conventional process window, which is determined through geometrical fidelity, geometric process window (GPW), does not account for lithography effects on electrical metrics such as delay, static noise margin (SNM), and power. In contrast to GPW, this paper introduces an electrical process window (EPW) which accounts for electrical specifications. Process parameters are considered within EPW if the performance (delay, SNM, and leakage power) of printed circuit is within desired specifications. Our experiment results show that the area of EPW is 1.5 to 8× larger than that of GPW. This implies that even if a layout falls outside geometric tolerance, the electrical performance of the circuit may satisfy desired specifications. In addition to process window evaluation, we show that EPW can be enlarged by 10% on average using gate length biasing and Vth push. We also propose approximate methods to evaluate EPW, which can be used with little or no design information. Our results show that the proposed approximation method can estimate more than 70% of the area of reference EPW. We also propose a method to extract representative layouts for large designs which can then be used to evaluate a process window, thereby improving the runtime by 49%.

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© 2011 Society of Photo-Optical Instrumentation Engineers (SPIE)

Citation

Tuck-Boon Chan ; Abde Ali Kagalwalla and Puneet Gupta
"Measurement and optimization of electrical process window", J. Micro/Nanolith. MEMS MOEMS. 10(1), 013014 (February 25, 2011). ; http://dx.doi.org/10.1117/1.3545822


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