Double patterning (DP) was investigated for logic layout by using a rigorous three-dimensional (3D) wafer-topography/lithography simulator with water immersion lithography. With increasing complexity of the DP process, the 3D wafer-topography effect of stack structure must be considered, because of its impact to lithography. The main purpose of this paper is to present how to optimize both process and design to ensure overlap and connectivity of split patterns by solving electro-magnetic field distribution in wafer substrate, as well as resist region. A process window was analyzed varying not only focus, dose, and split masking layers, but also considering topography of substrate stack structures, which cause local reflectivity variations. Arbitrary 45 nm logic layout including an L-shaped pattern was analyzed. The process window of the second litho step was analyzed. Due to the reflection from the hard mask (HM, result of the first litho step), the process window was restricted and became smaller. The other option suggests that swapping the first and second litho masks is a better choice, with respect to the impact of wafer topography. The optimization of the stack process condition was analyzed by using the contour plot of reflectivity, as functions of n, k, and thickness of materials inside the bottom anti-reflective coating. The concept of extended normalized image log slope considering local reflectivity variation from wafer process is able to explain the variation of resist sidewall slope and exposure latitude. Therefore, it is useful to analyze connectivity at the stitching point by using a 3D wafer-topography/lithography simulator and to optimize the combination of the DP process and layout stitching design. Furthermore, as a design of an advanced process, litho-develop litho-etch was simulated.