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Nanoimprint lithography and future patterning for semiconductor devices

[+] Author Affiliations
Tatsuhiko Higashiki, Tetsuro Nakasugi, Ikuo Yoneda

Toshiba Research and Development Center, Device Process Development Center, 8 Shinsugita-cho, Isogo-ku, Yokohama City 235-8522, Japan

J. Micro/Nanolith. MEMS MOEMS. 10(4), 043008 (November 15, 2011). doi:10.1117/1.3658024
History: Received March 29, 2011; Revised September 25, 2011; Accepted October 13, 2011; Published November 15, 2011; Online November 15, 2011
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Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed.

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© 2011 Society of Photo-Optical Instrumentation Engineers (SPIE)

Citation

Tatsuhiko Higashiki ; Tetsuro Nakasugi and Ikuo Yoneda
"Nanoimprint lithography and future patterning for semiconductor devices", J. Micro/Nanolith. MEMS MOEMS. 10(4), 043008 (November 15, 2011). ; http://dx.doi.org/10.1117/1.3658024


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