Nanoimprint lithography and future patterning for semiconductor devices

Tatsuhiko Higashiki; Tetsuro Nakasugi; Ikuo Yoneda

doi:10.1117/1.3658024

1 October 2011 Nanoimprint lithography and future patterning for semiconductor devices

Tatsuhiko Higashiki, Tetsuro Nakasugi, Ikuo Yoneda

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 10, Issue 4, 043008 (October 2011). https://doi.org/10.1117/1.3658024

Abstract

Nanoimprint lithography (NIL) has the potential capability of high resolution with critical dimension uniformity that is suited for patterning shrinkage, as well as providing a low cost advantage. However, the defectivity of NIL is an impediment to the practical use of the technology in semiconductor manufacturing. We have evaluated defect levels of NIL and have classified defectivity into three categories; nonfill defects, template defects, and plug defects. New materials for both the template and resist processes reduce these defects to practical levels. Electric yields of NIL are also discussed.

©(2011) Society of Photo-Optical Instrumentation Engineers (SPIE)

Citation Download Citation

Tatsuhiko Higashiki, Tetsuro Nakasugi, and Ikuo Yoneda "Nanoimprint lithography and future patterning for semiconductor devices," Journal of Micro/Nanolithography, MEMS, and MOEMS 10(4), 043008 (1 October 2011). https://doi.org/10.1117/1.3658024

Published: 1 October 2011

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