For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face nodes well below a 32-nm half pitch in the next 2 to 3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct-write variable-shaped beam equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a contact to be placed later. Up to now, the control of printed patterns such as line ends was achieved by a proximity effect correction mostly based on a dose modulation. This investigation of line end shortening (LES) includes multiple novel approaches, and contains an additional geometrical correction to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies using its state-of-the-art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production-like pattern in the range of our targeted critical structure dimensions in dense line space features smaller than 40 nm will be shown.