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Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes

[+] Author Affiliations
Bradley Morgenfeld

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Ian Stobert

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Ju Jin An

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Massud A. Aminpur

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Colin J. Brodsky

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Alan Thomas

IBM Systems and Technology Group, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Henning Haffner

Infineon Technologies NA Corporation, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Martin Ostermayr

Infineon Technologies NA Corporation, IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Hideki Kanai

Toshiba America Electronic Components, Inc.,.IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

Norman S. Chen

GLOBALFOUNDRIES U.S. Inc., IBM Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, New York 12533

J. Micro/Nanolith. MEMS MOEMS. 11(1), 013010 (Mar 19, 2012). doi:10.1117/1.JMM.11.1.013010
History: Received October 6, 2011; Revised December 16, 2011; Accepted January 18, 2012
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Abstract.  As 193-nm immersion lithography is extended indefinitely to sustain technology roadmaps, there is increasing pressure to contain escalating lithography costs by identifying patterning solutions that can minimize the use of multiple-pass processes. Contact patterning for the 32/28-nm technology nodes has been greatly facilitated by the just-in-time introduction of new process enablers that allow the support of flexible foundry-oriented ground rules alongside high-performance technology, without inhibiting migration to a single-pass patterning process. The incorporation of device-based performance metrics, along with rigorous patterning and structural variability studies, was critical in the evaluation of material innovation for improved resolution and CD shrink. Additionally, novel design changes for single patterning incorporating mask optimization efforts, along with new capability in data preparation, were assessed to allow for minimal impact of implementation of a single patterning contact process late in the 32-nm and 28-nm development cycles. In summary, this paper provides a comprehensive study of what it takes to turn a contact-level double-patterning process into a single-patterning process consisting of design and data manipulation, as well as wafer manufacturing aspects, together with many results.

© 2012 Society of Photo-Optical Instrumentation Engineers

Citation

Bradley Morgenfeld ; Ian Stobert ; Ju Jin An ; Massud A. Aminpur ; Colin J. Brodsky, et al.
"Escaping death: single-patterning contact printing for 32/28-nm logic technology nodes", J. Micro/Nanolith. MEMS MOEMS. 11(1), 013010 (Mar 19, 2012). ; http://dx.doi.org/10.1117/1.JMM.11.1.013010


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