An in-line inspection method for estimating defect resistances from the grayscale of voltage contrast in scanning electron microscope (SEM) images of manufactured patterns was developed. This method applies a circuit simulator to calculate the intensity of the secondary electrons according to an equivalent-circuit model considering the charge-up voltage on the patterns. To accurately estimate the resistance of defects formed in a device, first, the simulator was improved by considering the variation in defect resistance, which strongly depends on the differential voltage between the plug surfaces and the backside wafer. The defect resistances were obtained from the measured current-voltage (I-V) characteristics of the intentional defect on the standard calibration wafers, in which some incomplete-contact defects were systematically formed. Next, to consider the effect of the electronic characteristics of the pattern under the normal plugs on the grayscale, the I-V characteristics of the normal plugs were measured. The equivalent circuit of the simulator was improved by taking into account the measured I-V characteristics. The calibration curve for the manufactured patterns was calculated from the improved circuit simulator. Finally, the inspection method was applied to estimate the resistance of defects formed on an static random access memory (SRAM) pattern. The calculated calibration curve was used to estimate the defect resistance from the voltage contrast formed on the defects in the manufactured SRAM patterns. The accuracy of the estimation was about an order of magnitude.