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Shape slack: a design-manufacturing co-optimization methodology using tolerance information

[+] Author Affiliations
Shayak Banerjee

IBM Semiconductor Research & Development Corp., East Fishkill, New York 12533

Kanak B. Agarwal

IBM Austin Research Laboratory, 11501 Burnet Road, Austin, Texas 78758

Sani Nassif

IBM Austin Research Laboratory, 11501 Burnet Road, Austin, Texas 78758

Michael Orshansky

The University of Texas at Austin, Department of Electrical and Computer Engineering, Austin, Texas 78712

J. Micro/Nanolith. MEMS MOEMS. 12(1), 013014 (Feb 13, 2013). doi:10.1117/1.JMM.12.1.013014
History: Received July 25, 2012; Revised December 29, 2012; Accepted January 24, 2013
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Abstract.  The move to low-k1 lithography makes it increasingly difficult to print feature sizes that are a small fraction of the wavelength of light. With further delay in the delivery of extreme ultraviolet lithography, these difficulties will motivate the research community to explore increasingly broad solutions. We propose that there is significant research potential in studying the essential premise of the design/manufacturing handoff paradigm. Today this premise revolves around design rules that define what implementations are legal, and raw shapes, which define design intent, and are treated as a fixed requirement for lithography. In reality, layout features may vary within certain tolerances without violating any design constraints. The knowledge of such tolerances can help improve the manufacturability of layout features while still meeting design requirements. We propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes. We show how this can be done for two important implementation fabrics: (a) cell-library-based digital logic and (b) static random access memory. We further develop a tolerance-driven optical proximity correction algorithm that utilizes this shape slack information during mask preparation to ensure that all features prints within their shape slacks in presence of lithographic process variations. Experiments on 45 nm silicon on insulator cells using accurate process models show that this approach reduces postlithography delay errors by 50%, and layout hotspots by 47% compared to conventional methods.

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© 2013 Society of Photo-Optical Instrumentation Engineers

Citation

Shayak Banerjee ; Kanak B. Agarwal ; Sani Nassif and Michael Orshansky
"Shape slack: a design-manufacturing co-optimization methodology using tolerance information", J. Micro/Nanolith. MEMS MOEMS. 12(1), 013014 (Feb 13, 2013). ; http://dx.doi.org/10.1117/1.JMM.12.1.013014


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