Vertical NAND tips the standard transistor by 90 degrees. Instead of drain, gate, and source side by side along the surface of the wafer, the source is stacked on top of the gate, which is on top of the drain. Improved memory density comes from the ability to stack one transistor on top of another, fully using the third dimension for the first time. The implications for lithography are profound. The most critical dimensions, like the gate length, are no longer lithographically defined but rather are determined by film thicknesses. In fact, the lithography requirements are significantly relaxed: the first release of 3D flash chips is likely to require only 50-nm lithographic features (single patterning!). Lithography will be relaxed, but the etch requirements will be extremely challenging. The burden of transistor density improvements will no longer be upon lithography.