With the constant decrease of semiconductor device dimensions, gate line edge roughness (LER) becomes an important source of device variability. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during plasma etching. A plasma treatment is typically used to reduce the PR LER before the transfer. LER control at the nanometer scale also requires accurate measurements. We have recently developed a technique for LER measurement based upon atomic force microscopy (AFM). In this technique, the sample is tilted at about 45 deg and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The AFM technique is applied to the study of a pattern transfer into a gate stack starting from untreated PR, PR treated by conventional HBr plasma, and PR treated by plasma followed by a bake at 150°C. It is found that the plasma etching reduces the LER at each etching step. The reduction is more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an plasma treatment followed by a bake at 150°C.