Bonding is a key step in 3-D integrated circuit fabrication, occurring in multiple steps during the fabrication process. There will be a permanent bonding process during final assembly—which may be a wafer-to-wafer, chip-to-wafer, or chip-to-chip procedure—this will be using a process such as oxide-to-oxide, Cu-to-Cu, or adhesive bonding. In addition, there may be a temporary bonding step, where a device wafer is temporarily bonded to a handle wafer to permit the wafer thinning and other process steps. For the via-last process, the vias are formed after the wafer is thinned (note that in the via-first and via-mid processes, the vias are formed before or during the device and interconnect process). Each bonding process requires a strong, uniform bond, which is free of voids. These voids can occur from a number of chemical or mechanical processes including trapped air, solvent evaporation, outgassing from the polymer during curing, or particulates and surface nonuniformities. Such voids can interfere with the mechanical stability of the interface, causing unwanted local topology variation, nonuniform thinning, which can affect the TSV reveal process yield, or even delamination and breakage during thinning. Additionally, voids that occur during final assembly applications may interfere with electrical connectivity.