Special Section on Metrology and Inspection for 3-D Integrated Circuits and Interconnects

Metrology needs for through-silicon via fabrication

[+] Author Affiliations
Victor Vartanian

3D Center, SEMATECH, 257 Fuller Road, Suite 2200 Albany, New York 12203

Richard A. Allen

National Institute of Standards and Technology, Semiconductor & Dimensional Metrology Division, 100 Bureau Drive, Stop 8120, Gaithersburg, Maryland 20899-8120

Larry Smith

3D Center, SEMATECH, 257 Fuller Road, Suite 2200 Albany, New York 12203

Klaus Hummler

3D Center, SEMATECH, 257 Fuller Road, Suite 2200 Albany, New York 12203

Steve Olson

3D Center, SEMATECH, 257 Fuller Road, Suite 2200 Albany, New York 12203

State University of New York at Albany, College of Nanoscience and Engineering, Albany, New York 12203

Brian Sapp

3D Center, SEMATECH, 257 Fuller Road, Suite 2200 Albany, New York 12203

J. Micro/Nanolith. MEMS MOEMS. 13(1), 011206 (Feb 27, 2014). doi:10.1117/1.JMM.13.1.011206
History: Received August 28, 2013; Revised December 2, 2013; Accepted January 9, 2014
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Abstract.  This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of 5μm×50μm (diameter×depth), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits.

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© 2014 Society of Photo-Optical Instrumentation Engineers

Topics

Copper ; Metrology ; Silicon

Citation

Victor Vartanian ; Richard A. Allen ; Larry Smith ; Klaus Hummler ; Steve Olson, et al.
"Metrology needs for through-silicon via fabrication", J. Micro/Nanolith. MEMS MOEMS. 13(1), 011206 (Feb 27, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.1.011206


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