Special Section on Optical Lithography Extension Beyond the 14-nm Node

Sidewall profile engineering for the reduction of cut exposures in self-aligned pitch division patterning

[+] Author Affiliations
Frederick T. Chen

Industrial Technology Research Institute, 195, Section 4, Chung-Hsing Road, Chutung, Hsinchu, Taiwan

Wei-Su Chen

Industrial Technology Research Institute, 195, Section 4, Chung-Hsing Road, Chutung, Hsinchu, Taiwan

Ming-Jinn Tsai

Industrial Technology Research Institute, 195, Section 4, Chung-Hsing Road, Chutung, Hsinchu, Taiwan

Tzu-Kun Ku

Industrial Technology Research Institute, 195, Section 4, Chung-Hsing Road, Chutung, Hsinchu, Taiwan

J. Micro/Nanolith. MEMS MOEMS. 13(1), 011008 (Mar 25, 2014). doi:10.1117/1.JMM.13.1.011008
History: Received May 13, 2013; Revised February 16, 2014; Accepted March 4, 2014
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Abstract.  As 193-nm immersion lithography will likely be required to be extended beyond 40-nm half-pitch, multiple patterning lithography will become a necessity in that scenario. We present a cost-effective approach for double patterning with extendibility to sub-10-nm half-pitch division, which is a very promising candidate for advanced logic nodes. Spacers on sufficiently sloped sidewalls directly transferred from a low-contrast photoresist profile can be removed by anisotropic etching. Alternatively, spacer gaps for defining trenches may be prevented from penetrating to the substrate by the use of sloped sidewalls. These sloped sidewalls are defined by attenuated phase-shift mask features, which impart phase shifts other than 180 deg or 0 deg. Loop trimming and sidewall spacer definition are accomplished in a single photomask. In addition, there is now an extra ability to define random, arbitrary breaks in the spacer-defined pattern, without using an extra exposure for specified cuts. In this way, a single exposure using a modified attenuated phase-shift photomask, followed by a low-contrast development process around the sensitivity limit, is sufficient to pattern regularly arranged spacer-defined lines at fixed pitch while including some predetermined line cut locations.

© 2014 Society of Photo-Optical Instrumentation Engineers

Citation

Frederick T. Chen ; Wei-Su Chen ; Ming-Jinn Tsai and Tzu-Kun Ku
"Sidewall profile engineering for the reduction of cut exposures in self-aligned pitch division patterning", J. Micro/Nanolith. MEMS MOEMS. 13(1), 011008 (Mar 25, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.1.011008


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