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Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure

[+] Author Affiliations
Lingkuan Meng

Chinese Academy of Sciences, Institute of Microelectronics, Key Laboratory of Microelectronics Devices and Integrated Technology, 3 Beitucheng West Road, Chaoyang, Beijing 100029, China

Xiaobin He, Chunlong Li, Junjie Li, Peizhen Hong, Junfeng Li, Chao Zhao, Jiang Yan

Chinese Academy of Sciences, Institute of Microelectronics, Key Laboratory of Microelectronics Devices and Integrated Technology, 3 Beitucheng West Road, Chaoyang, Beijing 100029, China

J. Micro/Nanolith. MEMS MOEMS. 13(3), 033010 (Aug 27, 2014). doi:10.1117/1.JMM.13.3.033010
History: Received April 2, 2014; Revised July 23, 2014; Accepted August 1, 2014
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Abstract.  In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the poly-silicon gate etch based on the composite SiO2/Si3N4/SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α-Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.

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© 2014 Society of Photo-Optical Instrumentation Engineers

Citation

Lingkuan Meng ; Xiaobin He ; Chunlong Li ; Junjie Li ; Peizhen Hong, et al.
"Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure", J. Micro/Nanolith. MEMS MOEMS. 13(3), 033010 (Aug 27, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.3.033010


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