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Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations

[+] Author Affiliations
Sergio Gómez

Universitat Politècnica de Catalunya, Department of Electronic Engineering, Barcelona 08034, Spain

Francesc Moll

Universitat Politècnica de Catalunya, Department of Electronic Engineering, Barcelona 08034, Spain

Joan Mauricio

Universitat Politècnica de Catalunya, Department of Electronic Engineering, Barcelona 08034, Spain

J. Micro/Nanolith. MEMS MOEMS. 13(3), 033016 (Sep 16, 2014). doi:10.1117/1.JMM.13.3.033016
History: Received March 26, 2014; Revised August 13, 2014; Accepted August 25, 2014
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Abstract.  A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.

© 2014 Society of Photo-Optical Instrumentation Engineers

Citation

Sergio Gómez ; Francesc Moll and Joan Mauricio
"Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations", J. Micro/Nanolith. MEMS MOEMS. 13(3), 033016 (Sep 16, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.3.033016


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