Special Section on Holistic/Hybrid Metrology

Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

[+] Author Affiliations
Xiaoxiao Zhang

GlobalFoundries, 400 Stonebreak Road Extension, Malta, New York 12020, United States

Hua Zhou, Zhenhua Ge, Stefano Ventola

Applied Materials Inc., 2911 Route 9 Suite 3, Malta, New York, United States

Alok Vaid, Deepasree Konduparthi, Carmen Osorio

GlobalFoundries, 400 Stonebreak Road Extension, Malta, New York 12020, United States

Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, Maayan Bar-Zvi

Applied Materials Israel, 9 Oppenheimer Street, Rehovot 76705, Israel

J. Micro/Nanolith. MEMS MOEMS. 13(4), 041407 (Oct 01, 2014). doi:10.1117/1.JMM.13.4.041407
History: Received April 27, 2014; Revised August 9, 2014; Accepted August 28, 2014
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Abstract.  At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R2 equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

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© 2014 Society of Photo-Optical Instrumentation Engineers

Citation

Xiaoxiao Zhang ; Hua Zhou ; Zhenhua Ge ; Alok Vaid ; Deepasree Konduparthi, et al.
"Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope", J. Micro/Nanolith. MEMS MOEMS. 13(4), 041407 (Oct 01, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.4.041407


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