Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

Xiaoxiao Zhang; Hua Zhou; Zhenhua Ge; Alok Vaid; Deepasree Konduparthi; Carmen Osorio; Stefano Ventola; Roi Meir; Ori Shoval; Roman Kris; Ofer Adan; Maayan Bar-Zvi

doi:10.1117/1.JMM.13.4.041407

1 October 2014 Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope

Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Alok Vaid, Deepasree Konduparthi, Carmen Osorio, Stefano Ventola, Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, Maayan Bar-Zvi

Author Affiliations +

Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol. 13, Issue 4, 041407 (October 2014). https://doi.org/10.1117/1.JMM.13.4.041407

Abstract

At 1× node, a three-dimensional (3-D) FinFET process raises a number of new metrology challenges for process control, including gate height and fin height. At present, there is a metrology gap in inline in-die measurement of these parameters. To fill this metrology gap, in-column beam tilt has been implemented on Applied Materials V4i+ critical dimension scanning electron microscope for height measurement. Low-tilt (5 deg) and high-tilt (14 deg) beam angles have been calibrated to obtain the height and the sidewall angle information. Evaluation of its feasibility and production worthiness is done with applications in both gate height and fin height measurements. Transmission electron microscope correlation with an R² equal to 0.89 and a precision of 0.81 nm have been achieved on various in-die features in a gate height application. The initial fin height measurement shows less accuracy (R² being 0.77) and precision (1.49 nm) due to greater challenges brought by the fin profile, yet it is promising for the first attempt. Sensitivity to design of experiment offset die-to-die and in-die variations is demonstrated in both gate height and fin height. The process defect is successfully captured with inline gate height measurement. This is the first successful demonstration of inline in-die gate height measurement for a 14-nm FinFET process control.

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Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Alok Vaid, Deepasree Konduparthi, Carmen Osorio, Stefano Ventola, Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, and Maayan Bar-Zvi "Addressing FinFET metrology challenges in 1× node using tilt-beam critical dimension scanning electron microscope," Journal of Micro/Nanolithography, MEMS, and MOEMS 13(4), 041407 (1 October 2014). https://doi.org/10.1117/1.JMM.13.4.041407

Published: 1 October 2014

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