Special Section on Alternative Lithographic Technologies III

Design implications of extremely restricted patterning

[+] Author Affiliations
Kaushik Vaidyanathan

Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania 15213, United States

Renzhi Liu

Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania 15213, United States

Lars Liebmann

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Kafai Lai

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Andzrej J. Strojwas

Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania 15213, United States

Larry Pileggi

Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania 15213, United States

J. Micro/Nanolith. MEMS MOEMS. 13(3), 031309 (Oct 03, 2014). doi:10.1117/1.JMM.13.3.031309
History: Received June 17, 2014; Revised August 27, 2014; Accepted August 29, 2014
Text Size: A A A

Abstract.  Escalating manufacturing cost and complexity is challenging the premise of affordable scaling. With lithography accounting for a large fraction of wafer costs, researchers are actively exploring several cost-effective alternative lithographic techniques, such as directed self-assembly, self-aligned multiple patterning, etc. However, most of the alternative lithographic techniques are restrictive, and it is important to understand the impact of such pattering restrictions on system-on-chip (SoC) design. To this end, we artificially restricted all layers in a 14 nm process to be pure gratings and observed that the pure gratings approach results in an inefficient SoC design with several process integration concerns. To come up with a technology definition that is mindful of designer requirements, it is essential to undertake a holistic design technology co-optimization (DTCO) considering several SoC design elements, such as standard cell logic, static random access memory bitcells, analog blocks, and physical synthesis. Our DTCO on the IBM 14 nm process with additional 10- and 7-nm node-like pattern restrictions leads us to converge on a set of critical pattern constructs that are required for an efficient and affordable SoC design.

© 2014 Society of Photo-Optical Instrumentation Engineers

Citation

Kaushik Vaidyanathan ; Renzhi Liu ; Lars Liebmann ; Kafai Lai ; Andzrej J. Strojwas, et al.
"Design implications of extremely restricted patterning", J. Micro/Nanolith. MEMS MOEMS. 13(3), 031309 (Oct 03, 2014). ; http://dx.doi.org/10.1117/1.JMM.13.3.031309


Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging & repositioning the boxes below.

Related Book Chapters

Topic Collections

Advertisement
  • Don't have an account?
  • Subscribe to the SPIE Digital Library
  • Create a FREE account to sign up for Digital Library content alerts and gain access to institutional subscriptions remotely.
Access This Article
Sign in or Create a personal account to Buy this article ($20 for members, $25 for non-members).
Access This Proceeding
Sign in or Create a personal account to Buy this article ($15 for members, $18 for non-members).
Access This Chapter

Access to SPIE eBooks is limited to subscribing institutions and is not available as part of a personal subscription. Print or electronic versions of individual SPIE books may be purchased via SPIE.org.