Special Section on Continuation of Scaling with Optical and Complementary Lithography

Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip

[+] Author Affiliations
Kaushik Vaidyanathan

Carnegie Mellon University, Department of ECE, 5000 Forbes Avenue, Hamerschlag Hall 2114-D, Pittsburgh, Pennsylvania 15213, United States

Qiuling Zhu

Carnegie Mellon University, Department of ECE, 5000 Forbes Avenue, Hamerschlag Hall 2114-D, Pittsburgh, Pennsylvania 15213, United States

Lars Liebmann

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Kafai Lai

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Stephen Wu

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Renzhi Liu

Carnegie Mellon University, Department of ECE, 5000 Forbes Avenue, Hamerschlag Hall 2114-D, Pittsburgh, Pennsylvania 15213, United States

Yandong Liu

IBM, 2070 Route 52, Hopewell Junction, New York 12533, United States

Andzrej Strojwas

Carnegie Mellon University, Department of ECE, 5000 Forbes Avenue, Hamerschlag Hall 2114-D, Pittsburgh, Pennsylvania 15213, United States

Larry Pileggi

Carnegie Mellon University, Department of ECE, 5000 Forbes Avenue, Hamerschlag Hall 2114-D, Pittsburgh, Pennsylvania 15213, United States

J. Micro/Nanolith. MEMS MOEMS. 14(1), 011007 (Dec 30, 2014). doi:10.1117/1.JMM.14.1.011007
History: Received August 19, 2014; Accepted November 14, 2014
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Abstract.  For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology. Furthermore, we undertook such a holistic DTCO for all critical design elements such as embedded memory, standard cell logic, analog components, and physical synthesis in a 14-nm process. Measurements results from experimental designs in a representative 14-nm process from IBM demonstrate the efficacy of the proposed approach.

© 2015 Society of Photo-Optical Instrumentation Engineers

Citation

Kaushik Vaidyanathan ; Qiuling Zhu ; Lars Liebmann ; Kafai Lai ; Stephen Wu, et al.
"Exploiting sub-20-nm complementary metal-oxide semiconductor technology challenges to design affordable systems-on-chip", J. Micro/Nanolith. MEMS MOEMS. 14(1), 011007 (Dec 30, 2014). ; http://dx.doi.org/10.1117/1.JMM.14.1.011007


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