Microfabrication

Gate double patterning strategies for 10-nm node FinFET devices

[+] Author Affiliations
Hubert Hody, Tom Vandeweyer, Guillaume Boccardi, Kaidong Xu

IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Vasile Paraschiv

SC Etch Tech Solutions, Strada Oancea 3, Iaşi, Romania

David Hellin

Lam Research Corp., Kapeldreef 75, 3001 Leuven, Belgium

J. Micro/Nanolith. MEMS MOEMS. 14(1), 014504 (Mar 05, 2015). doi:10.1117/1.JMM.14.1.014504
History: Received September 11, 2014; Accepted February 3, 2015
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Abstract.  Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

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© 2015 Society of Photo-Optical Instrumentation Engineers

Citation

Hubert Hody ; Vasile Paraschiv ; David Hellin ; Tom Vandeweyer ; Guillaume Boccardi, et al.
"Gate double patterning strategies for 10-nm node FinFET devices", J. Micro/Nanolith. MEMS MOEMS. 14(1), 014504 (Mar 05, 2015). ; http://dx.doi.org/10.1117/1.JMM.14.1.014504


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