Lithography

Rigorous assessment of patterning solution of metal layer in 7 nm technology node

[+] Author Affiliations
Weimin Gao

Synopsys Inc., Technologielaan 11-0002B-3001 Leuven, Belgium

Imec, Kapeldreef 75, B-3001 Leuven, Belgium

Ivan Ciofi, Philippe Matagne, Werner Gillijns

Imec, Kapeldreef 75, B-3001 Leuven, Belgium

Yves Saad

Synopsys LLC, Thurgauerstrasse 40, Airgate BuildingCH-8050 Zurich, Switzerland

Michael Bachmann, Wolfgang Demmerle, Thomas Schmoeller

Synopsys GmbH, Karl-Hammerschmidt-Str. 34, 85609 Munich, Germany

Kevin Lucas

Synopsys Inc., 1301 South Mopac Expressway, Austin, Texas 78746, United States

J. Micro/Nanolith. MEMS MOEMS. 15(1), 013505 (Feb 19, 2016). doi:10.1117/1.JMM.15.1.013505
History: Received November 4, 2015; Accepted January 25, 2016
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Abstract.  In a 7 nm node (N7), the logic design requires a critical poly pitch of 42 to 45 nm and a metal 1 (M1) pitch of 28 to 32 nm. Such high-pattern density pushes the 193 immersion lithography solution toward its limit and also brings extremely complex patterning scenarios. The N7 M1 layer may require a self-aligned quadruple patterning (SAQP) with a triple litho-etch (LE3) block process. Therefore, the whole patterning process flow requires multiple exposure+etch+deposition processes and each step introduces a particular impact on the pattern profiles and the topography. In this study, we have successfully integrated a simulation tool that enables emulation of the whole patterning flow with realistic process-dependent three-dimensional (3-D) profile and topology. We use this tool to study the patterning process variations of the N7 M1 layer including the overlay control, the critical dimension uniformity budget, and the lithographic process window (PW). The resulting 3-D pattern structure can be used to optimize the process flow, verify design rules, extract parasitics, and most importantly, simulate the electric field, and identify hot spots for dielectric reliability. As an example application, the maximum electric field at M1 tip-to-tip, which is one of the most critical patterning locations, has been simulated and extracted. The approach helps to investigate the impact of process variations on dielectric reliability. We have also assessed the alternative M1 patterning flow with a single exposure block using extreme ultraviolet lithography (EUVL) and analyzed its advantages compared to the LE3 block approach.

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© 2016 Society of Photo-Optical Instrumentation Engineers

Citation

Weimin Gao ; Ivan Ciofi ; Yves Saad ; Philippe Matagne ; Michael Bachmann, et al.
"Rigorous assessment of patterning solution of metal layer in 7 nm technology node", J. Micro/Nanolith. MEMS MOEMS. 15(1), 013505 (Feb 19, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.1.013505


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