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Architectural strategies in standard-cell design for the 7 nm and beyond technology node

[+] Author Affiliations
Syed Muhammad Yasser Sherazi

KU Leuven, Department of Electrical Engineering, ESAT, Kasteelpark Arenberg 10, Leuven 3001, Belgium

Interuniversitair Micro Elektronica Centrum, Department of Logic Technologies, Kapeldreef 75, Heverlee 3001, Belgium

Bharani Chava, Peter Debacker, Marie Garcia Bardon, Pieter Schuddinck, Farshad Firouzi, Praveen Raghavan, Abdelkarim Mercha, Diederik Verkest, Julien Ryckaert

Interuniversitair Micro Elektronica Centrum, Department of Logic Technologies, Kapeldreef 75, Heverlee 3001, Belgium

J. Micro/Nanolith. MEMS MOEMS. 15(1), 013507 (Feb 25, 2016). doi:10.1117/1.JMM.15.1.013507
History: Received August 27, 2015; Accepted January 25, 2016
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Abstract.  Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.

© 2016 Society of Photo-Optical Instrumentation Engineers

Citation

Syed Muhammad Yasser Sherazi ; Bharani Chava ; Peter Debacker ; Marie Garcia Bardon ; Pieter Schuddinck, et al.
"Architectural strategies in standard-cell design for the 7 nm and beyond technology node", J. Micro/Nanolith. MEMS MOEMS. 15(1), 013507 (Feb 25, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.1.013507


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