Special Section on Extending VLSI and Alternative Technology with Optical and Complementary Lithography

Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process

[+] Author Affiliations
Yukihide Kohira

University of Aizu, School of Computer Science and Engineering, Tsuruga, Ikki-machi, Aizu-Wakamatsu, Fukushima 965-8580, Japan

Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka

Toshiba Corporation, Semiconductor and Storage Products Company, 2-5-1 Kasama, Sakae-ku, Yokohama 247-8585, Japan

Tomomi Matsui

Tokyo Institute of Technology, Department of Social Engineering, 2-12-1-W9-98 Ookayama, Meguro-ku, Tokyo 152-8550, Japan

Atsushi Takahashi

Tokyo Institute of Technology, Department of Communications and Computer Engineering, 2-12-1-S3-58 Ookayama, Meguro-ku, Tokyo 152-8550, Japan

J. Micro/Nanolith. MEMS MOEMS. 15(2), 021207 (Mar 11, 2016). doi:10.1117/1.JMM.15.2.021207
History: Received November 15, 2015; Accepted February 19, 2016
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Abstract.  LELECUT type triple patterning lithography is one of the most promising techniques in 14 nm logic node and beyond. To prevent yield loss caused by overlay error, LELECUT mask assignment, which is tolerant to overlay error, is desired. We propose a method that obtains a LELECUT assignment that is tolerant to overlay error. The proposed method uses positive semidefinite relaxation and randomized rounding technique. In our method, the cost function that takes the length of boundary of features determined by the cut mask into account is introduced.

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© 2016 Society of Photo-Optical Instrumentation Engineers

Citation

Yukihide Kohira ; Chikaaki Kodama ; Tomomi Matsui ; Atsushi Takahashi ; Shigeki Nojima, et al.
"Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process", J. Micro/Nanolith. MEMS MOEMS. 15(2), 021207 (Mar 11, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.2.021207


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