As a result of the continuously shrinking features of the integrated circuit, the overlay budget requirements have become very demanding. Historically, overlay has been performed using metrology targets for process control, and most overlay enhancements were achieved by hardware improvements. However, this is no longer sufficient, and we need to consider additional solutions for overlay improvements in process variation using computational methods. In this paper, we present the limitations of third-order intrafield distortion corrections based on standard overlay metrology and propose an improved method which includes a prediction of the device overlay and corrects the lens aberration fingerprint based on this prediction. For a DRAM use case, we present a computational approach that calculates the overlay of the device pattern using lens aberrations as an additional input, next to the target-based overlay measurement result. Supporting experimental data are presented that demonstrate a significant reduction of the intrafield overlay fingerprint.