Special Section on Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension

Lithographic imaging-driven pattern edge placement errors at the 10-nm node

[+] Author Affiliations
Jacek K. Tyminski, Stephen P. Renwick

Nikon Research Corporation of America, 1399 Shoreway Road, Belmont, California 94002, United States

Julia A. Sakamoto, Shane R. Palmer

Nikon Research Corporation of America, 12490 North Rancho Vistoso Boulevard, Suite 130, Oro Valley, Arizona 85737, United States

J. Micro/Nanolith. MEMS MOEMS. 15(2), 021402 (Mar 30, 2016). doi:10.1117/1.JMM.15.2.021402
History: Received August 12, 2015; Accepted February 9, 2016
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Abstract.  As new microelectronic designs are being developed, the demands on image overlay and pattern dimension control are compounded by requirements that pattern edge placement errors (EPEs) be at a single-nanometer levels. Scanner performance plays a key role in determining location of the pattern edges at different device layers, not only through overlay but also through imaging performance. The imaging contributes to edge displacement through the variations of the image dimensions and by shifting the images from their target locations. We discuss various aspects of advanced image control relevant to a 10-nm node integrated circuit design. We review a range of issues of pattern edge placement directly linked to pattern imaging. We analyze the impact of different pattern design and scanner-related edge displacement drivers. We present two examples of imaging strategies to pattern logic device metal layer cuts. We analyze EPEs of the cut images resulting from optimized layout design and scanner setup, and we draw conclusions on edge placement control versus imaging performance requirements.

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© 2016 Society of Photo-Optical Instrumentation Engineers

Topics

Scanners ; Metals

Citation

Jacek K. Tyminski ; Julia A. Sakamoto ; Shane R. Palmer and Stephen P. Renwick
"Lithographic imaging-driven pattern edge placement errors at the 10-nm node", J. Micro/Nanolith. MEMS MOEMS. 15(2), 021402 (Mar 30, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.2.021402


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