Achieving satisfactory overlay is increasingly challenging as feature sizes are reduced and allowable overlay budgets shrink to several nanometers and below. Overlay errors induced by wafer processing, such as film deposition and etching, constitute a meaningful fraction of overlay budgets. Wafer geometry measurements provide the opportunity to quantify stress-induced distortions at the wafer level and provide information that can be used in a feedback mode to alter wafer processing or in a feed-forward mode to set wafer-specific corrections in the lithography tool. In order for such feed-forward schemes based on wafer geometry to be realized, there is a need for mechanics models that relate in-plane distortion of a chucked wafer to the out-of-plane distortion of a wafer in a free state. Here, a simple analytical model is presented that shows the stress-induced component of overlay is correlated to a corrected local wafer slope metric for a wide range of cases. The analytical model is validated via finite element (FE) simulations of wafers with nonuniform stress distributions. Furthermore, FE modeling is used here to examine the effect of the spatial wavelength of stress variation on the connection between slope and the wafer stress-induced component of overlay.