Special Section on Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension

Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography

[+] Author Affiliations
John L. Sturtevant, Vlad Liubich, Rachit Gupta

Mentor Graphics Corporation, 8005 Southwest Boeckmann Road, Wilsonville, Oregon 97070, United States

J. Micro/Nanolith. MEMS MOEMS. 15(2), 021405 (Apr 27, 2016). doi:10.1117/1.JMM.15.2.021405
History: Received October 8, 2015; Accepted March 28, 2016
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Abstract.  Edge placement error (EPE) was a term initially introduced to describe the difference between predicted pattern contour edge and the design target for a single design layer. Strictly speaking, this quantity is not directly measurable in the fab. What is of vital importance is the relative edge placement errors between different design layers, and in the era of multipatterning, the different constituent mask sublayers for a single design layer. The critical dimensions (CD) and overlay between two layers can be measured in the fab, and there has always been a strong emphasis on control of overlay between design layers. The progress in this realm has been remarkable, accelerated in part at least by the proliferation of multipatterning, which reduces the available overlay budget by introducing a coupling of overlay and CD errors for the target layer. Computational lithography makes possible the full-chip assessment of two-layer edge to edge distances and two-layer contact overlap area. We will investigate examples of via-metal model-based analysis of CD and overlay errors. We will investigate both single patterning and double patterning. For single patterning, we show the advantage of contour-to-contour simulation over contour to target simulation, and how the addition of aberrations in the optical models can provide a more realistic CD-overlay process window (PW) for edge placement errors. For double patterning, the interaction of 4-layer CD and overlay errors is very complex, but we illustrate that not only can full-chip verification identify potential two-layer hotspots, the optical proximity correction engine can act to mitigate such hotspots and enlarge the joint CD-overlay PW.

© 2016 Society of Photo-Optical Instrumentation Engineers

Citation

John L. Sturtevant ; Vlad Liubich and Rachit Gupta
"Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography", J. Micro/Nanolith. MEMS MOEMS. 15(2), 021405 (Apr 27, 2016). ; http://dx.doi.org/10.1117/1.JMM.15.2.021405


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