The challenges outlined in Sec. 5 are substantial. For almost the entire history of the IC industry, such a reimagining of the fabrication of transistors at the device level would have been summarily dismissed. But these are interesting times. Industry conferences are full of sessions considering materials to replace silicon (carbon nanotubes, graphene, , and so on), steeper subthreshold devices (tunnelFETs), phase change materials (MEMristors), and nonvon Neuman computing solutions (the last three of which usually also require nonsilicon starting material). Such massive departures from silicon based, charge control, CMOS fabricated with optical lithography represent a long horizon endeavor, with many years (decades?) of research. In that light, the fact that we can generate such a specific, if incomplete, list of challenges to 3-D-ICs fabricated with MPL could be seen as an endorsement—the present approach leverages 60+ years of research into -type and -type contacts to silicon, gate stack engineering, drain, and source engineering, 450-mm starting material, CMP, design, layout and placement, and routing. We are able to judge the MPL approach so critically because it exists in a space we are familiar with; we have the callouses and scar tissue as evidence. Some of these tried and true notions may have to be discarded or adapted, but at least the issues are known. Adopting a nonsilicon based approach abandons much of this hard-won insight, and makes it difficult to assess the first order issues with a new technology, let alone the show-stopping, devil’s in the details issues which are more than enough to engulf and quash a seemingly promising direction.