Microfabrication

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

[+] Author Affiliations
Bo-Yuan Chen

National Chiao Tung University, Department of Materials Science and Engineering, Hsinchu, Taiwan

National Nano Device Laboratories, Hsinchu, Taiwan

Jiann-Lin Chen

I-Shou University, Department of Mechanical and Automation Engineering, Kaohsiung City, Taiwan

Chun-Lin Chu, Guang-Li Luo

National Nano Device Laboratories, Hsinchu, Taiwan

Shyong Lee

National Central University, Department of Mechanical Engineering, Chung-li, Taiwan

Edward Yi Chang

National Chiao Tung University, Department of Materials Science and Engineering, Hsinchu, Taiwan

J. Micro/Nanolith. MEMS MOEMS. 16(2), 024501 (May 23, 2017). doi:10.1117/1.JMM.16.2.024501
History: Received February 9, 2017; Accepted May 1, 2017
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Abstract.  This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide–semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

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© 2017 Society of Photo-Optical Instrumentation Engineers

Citation

Bo-Yuan Chen ; Jiann-Lin Chen ; Chun-Lin Chu ; Guang-Li Luo ; Shyong Lee, et al.
"Ge/IIIV fin field-effect transistor common gate process and numerical simulations", J. Micro/Nanolith. MEMS MOEMS. 16(2), 024501 (May 23, 2017). ; http://dx.doi.org/10.1117/1.JMM.16.2.024501


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