EUV lithography is viewed as a highly desirable technology for 5nm and 7nm node patterning cost reduction and process simplicity. However, for the 5nm and 7nm nodes EUV not only needs to function in a low-K1 resolution environment but has several new and complex patterning issues which will need accurate compensation by mask synthesis tools and flows. The main new issues are: long-range flare variation across the chip, feature dependent focus offsets due to high mask topography, asymmetry inducing shadowing effects which vary across the lens slit, significantly higher lens aberrations, illumination source changes (across the lens and with time) and new resist exposure mechanisms. These solutions must be successfully deployed at low K1 values and must be integrated together to create OPC/RET flows which have high resolution, high accuracy, and are fast to deploy. Therefore, the combined requirements of low-K1 resolution, full reticle correction accuracy and process window can be even more challenging than in current optical lithography mask synthesis flows. Advanced computational methods such as ILT and model-based SRAF optimization are well known to have considerable benefits in process window and resolution for low-K1 193 lithography. However, these methods have not been well studied to understand their benefits for lower-K1 EUV lithography where fabs must push EUV resolution, 2D accuracy and process window to their limits. In this paper, we investigate where inverse lithography methods can improve EUV patterning weaknesses vs. traditional OPC/RET. We first show how ILT can be used to guide a better understanding of optimal solutions for EUV mask synthesis. We then provide detailed comparisons of ILT and traditional methods on a wide range of mask synthesis applications.
|
