Paper
20 March 2018 3D memory: etch is the new litho
Christopher Petti
Author Affiliations +
Abstract
This paper discusses the process challenges and limitations for 3D NAND processes, focusing on vertical 3D architectures. The effect of deep memory hole etches on die cost is calculated, with die cost showing a minimum at a given number of layers because of aspect-ratio dependent etch effects. Techniques to mitigate these etch effects are summarized, as are other etch issues, such as bowing and twisting. Metal replacement gate processes and their challenges are also described. Lastly, future directions of vertical 3D NAND technologies are explored.
© (2018) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Christopher Petti "3D memory: etch is the new litho", Proc. SPIE 10589, Advanced Etch Technology for Nanopatterning VII, 1058904 (20 March 2018); https://doi.org/10.1117/12.2297131
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CITATIONS
Cited by 2 scholarly publications and 1 patent.
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KEYWORDS
Etching

Semiconducting wafers

Lithography

Manufacturing

Metals

Silicon

Reactive ion etching

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