A novel configurable VLSI architecture design of window-based image processing method

Hui Zhao; Hongshi Sang; Xubang Shen

doi:10.1117/12.2286998

6 March 2018 A novel configurable VLSI architecture design of window-based image processing method

Hui Zhao, Hongshi Sang, Xubang Shen

Proceedings Volume 10610, MIPPR 2017: Parallel Processing of Images and Optimization Techniques; and Medical Imaging; 1061006 (2018) https://doi.org/10.1117/12.2286998
Event: Tenth International Symposium on Multispectral Image Processing and Pattern Recognition (MIPPR2017), 2017, Xiangyang, China

Abstract

Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

Citation Download Citation

Hui Zhao, Hongshi Sang, and Xubang Shen "A novel configurable VLSI architecture design of window-based image processing method", Proc. SPIE 10610, MIPPR 2017: Parallel Processing of Images and Optimization Techniques; and Medical Imaging, 1061006 (6 March 2018); https://doi.org/10.1117/12.2286998

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KEYWORDS

Image processing

Very large scale integration

Multiplexers

Image filtering

Logic

Digital filtering

Clocks

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