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This paper introduces a 160×120 CMOS-based microbolometer array with a 35 μm pixel pitch operating in the 8-12 μm wavelength range, where the detector is fabricated with the LWIR-band CMOS infrared technology, shortly named as CIR, which is a patented novel approach that allows implementing microbolometers with standard CMOS and simple post-CMOS MEMS processes. Post-CMOS processes require only one mask lithography process and simple subtractive etching steps to obtain suspended microbolometer pixels, as opposed to the 8-15 mask deposition and etching processes in the widely used conventional surface micromachined microbolometer approaches that require the use of special high TCR materials like VOx or a-Si. Needing simple subtractive post-CMOS fabrication steps allows the CIR technology to be carried out in any CMOS and MEMS foundry in a truly fabless fashion, where industrially mature and Au-free wafer level vacuum packaging technologies can also be carried out, leading to cost advantage, simplicity, scalability, and flexibility. The implementation of an 80x80 FPA with 35 μm pixel pitch, namely MS0835, using the CIR technology was previously demonstrated, where wafer level vacuum packaged sensors with one side AR coating demonstrated to provide an NETD (Noise Equivalent Temperature Difference) values of 112 mK at 4 fps with f/1.1 optics. As a further study, this paper reports the implementation of the 160×120 FPA with a 35 μm pixel pitch, namely MS1635A using the CIR technology, where a 0.18 μm CMOS process is used. The sensor has a die size of 9.3 mm× 9.1 mm including the area for wafer level vacuum packaging and dissipates less than 50 mW at 30 fps while operating with 3.3V supply. The fabricated sensor is measured to provide a peak NETD of 161 mK, 117 mK, and 89 mK at 17 fps, 11 fps, and 4 fps, respectively, in a dewar environment with f/1.0 optics, i.e., it demonstrates a good performance for high volume low-cost consumer market applications like advanced presence detection and human counting. The CIR approach of MikroSens is scalable with the used CMOS processes, allowing to reduce the pixel pitch even further while increasing the array size and/or improving the sensor performance if necessary for IoT and various other low-cost, high volume markets.
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