Paper
23 March 2020 How to improve overlay of highly deformed 3D NAND wafers
Michael Kubis, Jing Jin, Steven Steen, Johan Beckers, Fayaz Shaikh, Bart van Schravendijk
Author Affiliations +
Abstract
3D NAND has become the mainstream technology to support bit growth of NAND Flash. The main challenge of 3D NAND is the increased level of wafer deformation as more layers are stacked vertically. This global deformation of the substrate leads to a significant degradation of overlay performance. One potential way to address this challenge is through bow compensation by wafer backside deposition. However, it turns out that standard backside processes sometimes do not improve overlay. This study investigates this phenomenon and explores how to counter high levels of wafer deformation in a way that overlay performance does not deteriorate. Scanner monitor wafers with etched reference marks have been modified to create a variety of global warp levels, covering a wafer bow range from +300μm (bowl shape) to -550μm (umbrella shape). Subsequently, several different backside deposition processes have been applied to these wafers. Flat reference wafers, warped wafers, and compensated wafers have been then measured on NXT scanners with different wafer tables. Non-linear overlay residuals of these wafers from about 1nm (flat reference wafers) to more than 30nm (uncompensated highly deformed wafers) have been measured. The obtained data reveal clear correlations between overlay, global wafer shape and backside deposition. A demonstration of the optimized overlay performance on wafers with large warpage values will be shown with a detailed analysis through absolute overlay metrology.
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Kubis, Jing Jin, Steven Steen, Johan Beckers, Fayaz Shaikh, and Bart van Schravendijk "How to improve overlay of highly deformed 3D NAND wafers", Proc. SPIE 11326, Advances in Patterning Materials and Processes XXXVII, 113260M (23 March 2020); https://doi.org/10.1117/12.2552042
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KEYWORDS
Semiconducting wafers

Overlay metrology

Scanners

Deposition processes

Optical alignment

Atomic force microscopy

Silicon

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