Progression of Logic Device and DTCO to enable advance scaling (Conference Presentation)

Satadru Sarkar; Bilal Chehab; Julien Ryckaert; Myung Hee Na; Alessio Spessot

doi:10.1117/12.2551690

25 March 2020 Progression of Logic Device and DTCO to enable advance scaling (Conference Presentation)

Satadru Sarkar, Bilal Chehab, Julien Ryckaert, Myung Hee Na, Alessio Spessot

Proceedings Volume 11328, Design-Process-Technology Co-optimization for Manufacturability XIV; 113280P (2020) https://doi.org/10.1117/12.2551690
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States

Abstract

CMOS technology scaling is enabled by multiple logic transistor architecture change from Planner to FinFET to Nanosheet and most recently Forksheet and CFET. Every architecture change has significant impact on the power-performance-area (PPA) scaling of any system on chip (SOC). A comprehensive Design-Technology-optimization (DTCO) methodology is needed to analyze this impact. In this paper technology scaling impact of this architecture change along with lithographic scaling will be analyzed from standard Cell to Block Level Place-Route to realize realistic PPA estimate.

Conference Presentation

Citation Download Citation

Satadru Sarkar, Bilal Chehab, Julien Ryckaert, Myung Hee Na, and Alessio Spessot "Progression of Logic Device and DTCO to enable advance scaling (Conference Presentation)", Proc. SPIE 11328, Design-Process-Technology Co-optimization for Manufacturability XIV, 113280P (25 March 2020); https://doi.org/10.1117/12.2551690

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