Presentation + Paper
20 October 2020 Patterning solutions for NTD contact hole levels in advanced DRAM nodes
Author Affiliations +
Abstract
Advanced DRAM technology relies heavily on 193nm immersion lithography. Negative tone develop (NTD) layers are becoming increasingly important particularly in nodes below 20nm. NTD is particularly useful for patterning holes on the wafer. Cut layers for multi-patterning (MP) applications and bit line contact structures are common uses of NTD in DRAM. Patterning these structures pose lithographic challenges around process window (PW), layer-to-layer overlay, and critical dimension (CD) control. The mask plays a critical role in optimizing all of these attributes. In this paper, we explore multiple mask enhancements to optimize wafer performance for NTD contacts. These include mask process and mask blank conditions, as well as a data enhancement technique generally known as mask process correction (MPC). Specifically, we implement a litho-aware MPC Application (LAMA) to optimize mask pattern fidelity. Finally, we harmonize these mask enhancements with optimizations to wafer exposure conditions and optical proximity correction (OPC) to demonstrate capability improvement in NTD contact lithography.
Conference Presentation
© (2020) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Green, Tsu-Wen Huang, Mohamed Ramadan, Hung-Chang Szu, Yeu Dong Gau, Chih-Ying Tsai, Young Ham, Chun-Cheng Liao, Lucien Bouchard, Eric Huang, Wei-Cheng Shiu, and Chris Progler "Patterning solutions for NTD contact hole levels in advanced DRAM nodes", Proc. SPIE 11518, Photomask Technology 2020, 115180N (20 October 2020); https://doi.org/10.1117/12.2574713
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KEYWORDS
Photomasks

Optical lithography

Semiconducting wafers

Lithography

Optical proximity correction

193nm lithography

Critical dimension metrology

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