Design process integration enabling the productivity enhancement for nanoimprint lithography

Sachiko Kobayashi; Satoshi Mitsugi; Katsuyoshi Kodera; Kazuya Fukuhara; Anupam Mitra; Koki Ueha; Katsuya Abe; Motofumi Komori; Shingo Kanamitsu; Takuya Kono

doi:10.1117/12.2614319

26 May 2022 Design process integration enabling the productivity enhancement for nanoimprint lithography

Sachiko Kobayashi, Satoshi Mitsugi, Katsuyoshi Kodera, Kazuya Fukuhara, Anupam Mitra, Koki Ueha, Katsuya Abe, Motofumi Komori, Shingo Kanamitsu, Takuya Kono

Author Affiliations +

Proceedings Volume 12052, DTCO and Computational Patterning; 1205208 (2022) https://doi.org/10.1117/12.2614319
Event: SPIE Advanced Lithography + Patterning, 2022, San Jose, California, United States

Abstract

Ultraviolet nanoimprint lithography (NIL) is a simple contact process that is attractive and promising process for high pattern fidelity, without blurring effect due to light scattering or acid diffusion in the resist. Specifically, complicated 3D patterns, fine 2D patterns, and fine 1D patterns can be formed in fewer process steps compared to those for optical lithography. On the other hand, there are fewer adjustment knobs for process tuning in NIL; therefore, it is necessary to introduce design restrictions customized for NIL to improve the process margin. Since pattern transfer is performed through filling of a resist having a finite volume, a design constraint considering filling property is required to reduce defect density and improve throughput. In this study, two types of design constraints are examined to address the NIL process margin problem. One is a NIL alignment mark design that satisfies both signal strength and filling characteristics. The other is a combination of the pattern coverage rule with wafer topography that achieves good filling characteristics under various substrate unevenness conditions. Experiment results were interpolated with NIL process simulations and common areas under various conditions were extracted to identify the design rules for achieving large process margins. By using a design flow that considers these rules, we believe that high volume manufacturing (HVM) yields can be increased considerably by reducing yield issues and reducing redesign loops.

Conference Presentation

Citation Download Citation

Sachiko Kobayashi, Satoshi Mitsugi, Katsuyoshi Kodera, Kazuya Fukuhara, Anupam Mitra, Koki Ueha, Katsuya Abe, Motofumi Komori, Shingo Kanamitsu, and Takuya Kono "Design process integration enabling the productivity enhancement for nanoimprint lithography", Proc. SPIE 12052, DTCO and Computational Patterning, 1205208 (26 May 2022); https://doi.org/10.1117/12.2614319

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