Poster + Paper
28 April 2023 Cost analysis of device options and scaling boosters below the A14 technology node
G. Mirabelli, A. Vandooren, C. Roda Neve, V. V. Gonzalez, H. Mertens, A. Farokhnejad, P. Schuddinck, G. Murdoch, S. M. Salahuddin, O. Zografos, L. Ragnarsson, P. Weckx, Z. Tokei, G. Hellings, J. Ryckaert
Author Affiliations +
Conference Poster
Abstract
The saturation in dimensional scaling has clearly impacted the semiconductor technology roadmap. The extension of patterning cliffs through new tools and multi-patterning lithography, as well as the introduction of innovative scaling boosters is helping in optimally scaling the Power-Performance-Area (PPA) metrics. However, because of the increase in the process complexity and reduced area benefits, manufacturing cost is increasing. Therefore, moving to a PPA-Cost (PPAC) methodology to monitor and analyze the cost of a technology is becoming increasingly necessary.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
G. Mirabelli, A. Vandooren, C. Roda Neve, V. V. Gonzalez, H. Mertens, A. Farokhnejad, P. Schuddinck, G. Murdoch, S. M. Salahuddin, O. Zografos, L. Ragnarsson, P. Weckx, Z. Tokei, G. Hellings, and J. Ryckaert "Cost analysis of device options and scaling boosters below the A14 technology node", Proc. SPIE 12495, DTCO and Computational Patterning II, 124951K (28 April 2023); https://doi.org/10.1117/12.2656456
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KEYWORDS
Semiconducting wafers

Metals

Back end of line

Optical lithography

Silver

Front end of line

Nanosheets

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