Paper
5 October 2023 Test pattern generation by optimization of the feature space signature
Author Affiliations +
Proceedings Volume 12802, 38th European Mask and Lithography Conference (EMLC 2023); 1280207 (2023) https://doi.org/10.1117/12.2675601
Event: 38th European Mask and Lithography Conference, 2023, Dresden, Germany
Abstract
Background: Well-designed test patterns are required to ensure a robust patterning involving mask, lithography and etch. They are expected to anticipate potential process challenges while representing well the layout diversity. Problem: We expect good test patterns to have a high design space coverage with minimal redundancy. Is it possible to get optimal design contents while keeping a small footprint and following the design rules? Approach: In this work, after defining specific optical and geometrical features and discretizing the pattern as a binary matrix, we propose to use the signature of the pattern in the feature space to assign a score measuring the usefulness of the pattern. The score is used as a cost function to drive an iterative optimization of the pattern shape based on a differential evolution algorithm. Conclusion: We demonstrated how to generate compact test patterns with high design diversity customized to specific applications that should help to anticipate, represent or monitor well process challenges.
© (2023) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Francois Weisbuch and Jirka Schatz "Test pattern generation by optimization of the feature space signature", Proc. SPIE 12802, 38th European Mask and Lithography Conference (EMLC 2023), 1280207 (5 October 2023); https://doi.org/10.1117/12.2675601
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Design and modelling

Matrices

Design rules

Lithography

Etching

Feature extraction

Optical lithography

RELATED CONTENT

DSA-aware assist features
Proceedings of SPIE (March 19 2015)
Crossing the divide between lithography and chip design
Proceedings of SPIE (July 12 2002)
Impact of mask errors on full chip error budgets
Proceedings of SPIE (July 26 1999)

Back to Top