In prior work, as a means to overcome computational cost while maintaining similar ILT lithographic quality, we presented full-chip layout synthesis with curve-based OPC as a complimentary option with curvilinear ILT. However, there are an increasing number of different quality determinations, cost constraints and orthogonal solutions needed for curvilinear mask and target correction to meet the requirements for different layers (L/S, CH/Via/Cut-mask), devices (logic, DRAM, Flash) and lithographic applications (DUV, EUV, photonics, flat-panel display, High NA EUV), etc. In this paper, we will share a spectrum of advances for curvilinear masks and targets by ILT, and integrated curve-based ILT/OPC. These varied solutions can achieve the quality and computational cost requirements for the different application areas previously listed. Additionally, we will also describe new advancements in adjacent areas of the curvilinear mask ecosystem for MRC, MEC, etch and data volume reduction.
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