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Nanosheet device architectures such as complementary FET (CFET) are candidates to replace FinFET, improving device performance while allowing a higher density of devices for a similar footprint. Two main challenges can be highlighted in the definition of the active area (AA) patterning for CFET. First the presence of stacked nanosheets generates the need for a higher aspect-ratio compared to FinFET. Secondly, the nanosheets layers, composed of silicon and silicon-germanium with varied thicknesses and concentrations, require new approaches in terms of process definition and control. The first results of an active area patterning for a full CFET device have been demonstrated at imec. Thicker nanosheet stacks are patterned opening the path to the creation of a complete CFET device.
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(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.
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V. Brissonneau, Il Gyo Koo, M. Hosseini, D. Batuk, A. Veloso, G. Mannaert, F. Lazzarino, "Active area patterning for CFET: nanosheet etch," Proc. SPIE 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, 1295804 (9 April 2024); https://doi.org/10.1117/12.3012322